module top
(
    input          input_clk,     
    input          sys_rst_n,
    output         [7:0] out        
);

wire  sys_clk;   
wire  uart_clk;  
wire  extlock;   

//		Clock name	| Frequency 	| Phase shift
//		C0        	| 100.000000MHZ	| 0  DEG     
pll u_pll(
    .refclk   (input_clk ),
    .reset    (~sys_rst_n),
    .extlock  (extlock 	 ),
    .clk0_out (O_clk0    )
); 

assign sys_clk = O_clk0; 


reg  [7:0] wr_data;     //synthesis keep;
reg  [9:0] wr_addr;     //synthesis keep;
reg  wr_en;             //synthesis keep;

wire [7:0] rd_data;     //synthesis keep;
reg  [9:0] rd_addr;     //synthesis keep;
reg  rd_en;             //synthesis keep;

bram
ram_inst( 
  .dia  (wr_data), 
  .addra(wr_addr), 
  .cea  (wr_en  ), 
  .clka (sys_clk),

  .dob  (rd_data), 
  .addrb(rd_addr), 
  .ceb  (rd_en  ), 
  .clkb (sys_clk)
);

//write
reg [2:0] wr_cnt;
always @(posedge sys_clk or negedge sys_rst_n) begin
  if (!sys_rst_n) begin
    wr_cnt <= 'd0;
  end
  else begin
    wr_cnt <= wr_cnt + 1;
  end
end

always @(posedge sys_clk or negedge sys_rst_n) begin
  if (!sys_rst_n) begin
    wr_en <= 1'b0;
  end
  else if(wr_cnt[0] == 1'b1) begin
    wr_en <= 1'b1;
  end
  else begin
    wr_en <= 1'b0;
  end
end

always @(posedge sys_clk or negedge sys_rst_n) begin
  if (!sys_rst_n) begin
    wr_addr <= 'd0;
  end
  else if((wr_cnt[0] == 1'b0) & (wr_addr < 1023)) begin
    wr_addr <= wr_addr + 1;
  end
end

always @(posedge sys_clk or negedge sys_rst_n) begin
  if (!sys_rst_n) begin
    wr_data <= 'd0;
  end
  else if(wr_cnt[0] == 1'b0) begin
    wr_data <= wr_data + 1;
  end
end



//read
reg [5:0] cnt;

always @(posedge sys_clk or negedge sys_rst_n) begin
  if (!sys_rst_n) begin
    cnt <= 'd0;
  end
  else begin
    cnt <= cnt + 1;
  end
end

always @(posedge sys_clk or negedge sys_rst_n) begin
  if (!sys_rst_n) begin
    rd_en <= 1'b0;
  end
  else if(cnt[0] == 1'b1) begin
    rd_en <= 1'b1;
  end
  else begin
    rd_en <= 1'b0;
  end
end

always @(posedge sys_clk or negedge sys_rst_n) begin
  if (!sys_rst_n) begin
    rd_addr <= 'd0;
  end
  else if(cnt[0] == 1'b0) begin
    rd_addr <= rd_addr + 1;
  end
  else if(rd_addr == 100) begin
    rd_addr <= 'd0;
  end
end

endmodule

